N-Tuple Compression: A Novel Method for Compression of Branch Instruction Traces

Branch predictors and processor front-ends have been the focus of a number of computer architecture studies. Typically they are evaluated separately from other components using trace-driven simulation based on instruction traces. To offer a faithful representation of processor’s workload the traces are very large, and hence difficult to manage if kept in uncompressed form. In order to reduce simulation overhead due to the processing of non-branch instructions, we propose a new form of instruction trace, the Branch Instruction Trace (BIT), suitable for simulation of dynamic branch prediction mechanisms, fetch engines, and trace caches. A novel method for lossless trace compression, which can be applied to both ASCII and binary BIT traces, is also introduced. The proposed method relies on the trace record table (TRT) consisting of unique trace records. The trace size can be reduced by replacing each trace record by its ID in the TRT, since the number of unique trace records is much less than the trace length. We further extend this idea and replace an entire N-tuple of BIT records with its ID from the N-Tuple Record Table (N-TRT). The analysis shows that for a subset of SPEC CPU2000 benchmarks 8-tuple replacement yields significant compression ratio (40 for binary traces and 32-43 for ASCII traces), while keeping N-TRT size reasonable. When combined with the common compression tools such as gzip the compression ratio is 195-3888 for binary, and 306-4604 for ASCII traces, while gzipped-only traces achieve compression ratio 20201 for binary, and 20-216 for ASCII traces.